Referring to FIG. 1, it shows a prior art of switching power supply 100 that is adapted to be AC-DC conversion and LED driving. The switching power supply 100 comprises a switching power supply control device 101, a resistor R1, and a power MOS device 102.
Still referring to FIG. 1, during the high-voltage startup of the switching power supply 100, a high-voltage terminal HV supplies a startup current to a power supply terminal VCC of the switching power supply control device 101 via the resistor R1, to finish the high-voltage startup of the switching power supply 100. After the high-voltage startup, the high-voltage terminal HV further supplies power to the power supply terminal VCC of the switching power supply control device 101 via the resistor R1. In operation, a drive terminal DRV of the switching power supply control device 101 drives a gate G of the high-voltage device 102, to provide a power driving output at a source S of the power device 102 or at the high-voltage terminal HV.
Referring to FIG. 2, it shows a schematic diagram of a layout 201 of the power device 102 within the switching power supply 100 in FIG. 1. The power device 102 is a high-voltage MOS device.
As shown in FIG. 1 and FIG. 2, on the layout 201 of the high-voltage MOS device 102, a bonding pad for the gate G and a bonding pad for the source S are located on a front side, and a bonding pad for the drain D is located on a back side. The three bonding pads may function to provide a power driving output of the high-voltage MOS device 102.
Referring to FIG. 3, it shows a longitudinal cross-sectional view along a direction AA′ in FIG. 2.
As shown in FIG. 3, taking an N-type device as an example, the high-voltage MOS device includes: an N-type epitaxial region 306 of the MOS transistor, wherein the epitaxial region 306 is led out by an electrode 301 to form a drain of the MOS transistor; a P-well 302 of the MOS transistor; an N-type doped region 305 of the MOS transistor; a P-type doped region 309 of the MOS transistor, wherein the P-well 302, the P-type doped region 309 and the N-type doped region 305 are shorted via an electrode 303 to form a source of the MOS transistor; and a gate 304 of the MOS transistor. With regard to the whole structure of the device, the P-well 302, the N-type doped region 305, the P-type doped region 309 and the gate 304, etc., are formed in a cell portion 308. The cell portion 308 is a current conduction region of the device, and is an active region. The power device may be formed by a multitude of cell portions 308. There is a high-voltage ring 307 outside an edge of the cell portion 308. The high-voltage ring 307 may include a plurality of P-type doped regions 310, and may correspond to the region 207 shown in FIG. 2. The internal structure of the above device and the operation principles thereof are well known in the art, and will not be described in detail.
In connection with FIG. 1 and FIG. 3, the electrode 301 is coupled to the high-voltage terminal HV of the switching power supply 100, and the gate 304 is coupled to the driving terminal DRV of the switching power supply 100. When a voltage applied to the gate 304 is higher than a threshold voltage, the surface of the P-well 302 is inversed to form a channel, such that the source and the drain of the MOS transistor are electrically coupled to provide a power output.
In the scheme of FIG. 1, the high-voltage startup of the switching power supply 100 and the power supply for the supply terminal VCC of the switching power supply control device 101 are performed via the resistor R1. Since a current always flows through the resistor R1, there is a tradeoff between the startup time and the standby power consumption: if the resistance of the resistor R1 is small, during the high-voltage startup, the high-voltage terminal HV supplies a high current to the supply terminal VCC via the resistor R1, resulting a short startup time of the switching power supply 100, but after the high-voltage startup, the large current flowing through the resistor R1 causes high standby power consumption for the switching power supply 100; otherwise, if the resistance of the resistor R1 is large, during the high-voltage startup, the high-voltage terminal HV supplies a low current to the supply terminal VCC via the resistor R1, resulting a long startup time of the switching power supply 100, but after the high-voltage startup, the small current flowing through the resistor R1 causes low standby power consumption for the switching power supply 100.
To balance the startup time and the standby power consumption, in practice, the resistor R1 is generally chosen at an order of MΩ. Even so, when the voltage at the high-voltage terminal HV is at 220 VAC, the power consumption of the resistor R1 will be more than ten mW, up to hundreds of mW.
As above, the switching power supply 100 which performs the high-voltage startup of the switching power supply 100 and power supply for the supply terminal VCC of the switching power supply control device 101 via the resistor R1 in the prior art cannot both reduce the startup time, and decrease the standby power consumption.
For the problem above, there is proposed a solution in the prior art to add a depletion-mode device for startup, as shown in FIG. 4. On the basis of the existing switching power supply, the switching power supply 400 in FIG. 4 adds a high-voltage startup device 403 to expedite the high-voltage startup procedure of switching power supply 400, wherein the high-voltage startup device 403 is a depletion-mode MOS transistor. After the high-voltage startup, the high-voltage startup device 403 is turned off to reduce the standby power consumption of switching power supply 400, thereby improving the efficiency of the switching power supply 400.
In the prior art, the high-voltage startup device 403 is used as a separate device, primarily for high-voltage signal processing and control. Since the high-voltage startup device 403 is a separate device, the switching power supply 400 needs an extra component, which increases the complexity and cost of the system.
In view of the above problems, the Chinese patent application CN201210492874.4 proposes an integrated device, wherein a switching power supply control portion of a low voltage section is integrated with a high-voltage HVMOS section and a JFET, which may be achieved by a high-voltage BCD process. However, this scheme needs to be achieved by the high-voltage BCD process, such that the process for the whole chip is complex and costly. Moreover, due to the power consumption limitation of HVMOS devices in the high-voltage BCD process, this scheme can not be applied to high power scenarios.